Plated wire memory

ABSTRACT

There is disclosed herein a quaternary alloy plating composition for a NDRO (non-destructive read-out) magnetic memory wire comprising by weight 77.3% Ni, 18.2% Fe, 3.5% Co, 1.0% P and substantially non-magnetostrictive.

United? Siaies Patent 1191 Diguiiio Dec. 10, 1974 PLATED WERE MEMORY OTHER PUBLICATIONS [75 1 I. TSU, A New Cobalt-Nickel Sulfamate Bath," Plat- [73] Assignee: Sperry Rand Corporation, New ing, April 1961, pages 379-381.

York, NY.

[22] Filed: June 29, 1973 Primary ExaminerJohn H. Mack Assistant ExaminerAaron Weisstuch [21] Appl' 375266 Attorney, Agent, or Firm-Rene A. Kuypers [52] US. Cl 204/28, 204/43 T, 204/43 P,

340/174 PW [57] ABSTRACT [51] Int. Cl. C23b 5/58, C23b 5/32 There i di l d herein a quaternary alloy plating [58] Fleid 0f Search 204/28, 43 T, 43 P, 12, composition f a NDRO (non destructive read out) 204/13 magnetic memory wire comprising by weight 77.3% Ni, 18.2% Fe, 3.5% Co, 1.0% P and substantially non- [56] References Cted magnetostrictive. UNITED STATES PATENTS 3,354,059 11/1967 Koretzky 204/12 6 Clam, 5 Draw Flgures WATER RINSE l2 l6 I8 20 10 11 g l L l HQr 1 r 1 er 1 .r m m 0 14 I 14 14 14 SUBSTRATE ELECTRO- COPPER ANNEALING CUT AND REEL CLEANER PLATING FURNACE PACKAGE w PU3H|NG ACID MAGNETIC TEST ROLLERS ETCHANT PLATING PATENTED 91974 3,853.7 l 7 SHEET 10F 2 WATER RINSE l2 l6 I8 20 IO II i k L O T I4 M T I4 I4 T SUBSTR ELECTRO- COPPER ANNEALING AND REE CLEANER PLATING FURNACE KAGE w PUSHING ACID MAGNETIC TEST ROLLERS ETCHANT PLATING SOLUTION IN I-Cu DEPOSITION ANODE CONNECTION I-ELECTROCLEAN I-BIAS TESTER [30 I0 l l O 1- INCH-a l v CATHODE REEL CONNECTION Fig. 2 OUT NDRO | l oPERATING POINT OPERATING I A "WINDOW" WORD CURRENT I BIT cuRRENT T SINGLE wRITE SWITCHING] CURVE FOR THRESHOLD V OUTPUT (PRIOR ART) BIT CURRENT WALL MOTION THRESHOLD PATENTEL LEE] 0 I974 SHEET 2 OF 2 PLATED WIRE MEMORY BACKGROUND OF THE INVENTION Field of the Invention DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. 1 in greater detail, there is This invention reates to the field of computer mem Shown a reel having several-feet of wire substrate 11 ries and in particular to the magnetic type that operates in the NDRO mode.

Description of the Prior Art The known pertinent prior art is contained in the IEEE Transactions on Magnetics, Vol. Mag-5, No. 4, December, 1969, pp. 728751 by .I. S. Mathias and G. A. Fedde, and US. Pat. Nos. 3,370,929 and 3,549,507.

The recognized shortcoming of the known prior art plated wires has been their narrow operating margins. This means that the plated wires with such operating characteristics are able to withstand only limited current variations along the bit and word lines. This is a serious shortcoming since such wires are rejected during the manufacturing process and therefore the production yields are decreased and the unit cost increased. In other words, plated wires manufactured with limited operating margins make it difficult to compete in the marketplace and hence, are not viable memory devices.

The instant invention is designed to provide a NDRO plated wire memory element with a wider range of magnetic characteristics than exists in the prior art. In particular, the present invention provides wires having an increased wall motion threshold. The wall motion threshold is the upper limit of bit current (current down the wire in the write mode) allowed in the operation of the plated wire. If the wall motion threshold is exceeded, information stored along the wire will be destroyed.

The present invention also is designed to provide a higher degree of uniformity along the length of the wire and a larger operating region so that better utilization of the wire can be obtained. By uniformity is meant that the magnetic parameters of the wire have reduced variations along the length of the wire.

The gist of the invention is accordingly a new magnetic plating composition composed of nickel, iron, cobalt and phosphorous on a uniformly rough or spherular, hereinafter referred to as caviar intermediate layer. The caviar surface is formed on a smooth, mirror-like, non-magnetic wire substrate.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic representation of the plating process utilized in the invention;

FIG. 2 depicts in schematic form the various currents applied during the plating process as well as a schematic of the call arrangement which is utilized;

FIG. 3 is a view of a smooth, drawn wire as initially provided during the plating operation at 3,000 magnification wherein 3 millimeters thereon equal I micron (N.00004 in.)

FIG. 4 is a view of the uniformly rough or intermediate surface plated upon the substrate shown in FIG. 3 at 3,000 magnification wherein 3 millimeters thereon equals I micron; and

FIG. 5 depicts a simplified switching diagram of a bit along the plated wire provided by the present invention as well as for the prior art plated wire.

wound around its circumference. The substrate 11 is made of a non-magnetic material such as berylliumcopper or phosphor-bronze alloy on the order of about 2-5 mils in diameter. Prior to placing the substrate 11 on the reel 10, it may be electropolished in accordance with well established prior art practices to remove troublesome defects such as die marks, gouges and inclu-' sions, refractory oxides, etc..

As the plater arrangement shown in FIG. 1 is placed in operation, the smooth substrate 11 is first electrocleaned at station 12 in order to remove grease, dirt and extraneous matter. Well established prior art materials and procedure are utilized during this step of the operation. The schematic shown in FIG. 2 indicates that during the electrocleaning step, current (see Table III) is supplied to the cell between the anode and cathode. The actual cell construction will be discussed in greater detail hereinafter. As is readily understood, the electrical current path is provided through the anode connection, the electrolyte, the substrate 11 to the cathode connection or ground. Following the electrocleaning operation, the substrate 11 is rinsed at station 14', following which it is subjected toan acid etch at station 16 and further rinsed at station 14". The acid etch is utilized to dissolve any residual metallic oxides still remaining on the substrate after the electroclean step.

Following electrocleaning, acid etch and water rinses, the substrate 1 l is subjected to a copper plating operation at station 18. The purpose of the copper plating is to provide a uniformly rough (as opposed to a randomly rough) surface on the smooth wire substrate. This surface has been described as nodular or caviar and is shown in magnified form in FIG. 4. The nodular copper surfaces are typically plated to a thickness of approximately 5-10.000 A. The copper can be deposited from a pyrophosphate copper solution, or preferably from a high-efficiency cyanide bath of the composition given in Table I.

It should be noted that the pH can be adjusted with KOH.

In the instant invention, the cyanide solution is preferred. Referring again to FIG. 2, there is shown in schematic form the electrical connection for the copper deposition step. The current parameters applied during this step of the operation is shown in Table III.

After rinsing the substrate 1 l at station 14'", the nodular covered wire is subjected to a magnetic plating process at station 20. Formulations for useful Permalloy electrolytes are given in Table II below.

TABLE II zation of the magnetic film circumferentially around the wire. In this situation, the circumferential direction Range P f n d is known as the EASY axis direction. A direction 90 removed from the EASY direction is known as the g frj g igg i 2??? HARD direction. During the write or read cycle of the cosofit-mzow) g 5 plated wire memory, the magnetization is rotated to Boric acid is) 0 some angle less than 90. Suitable conditions for plating 1223:1222ifl zg upon substrates are described in Table III below. Water (I) i 1 Referring now to the plated wire switching diagram gi' gf gc (g) 51 0 i 10 of FIG. 5, the bit current is shown as the absicissa and Ratio Ni/Fe 50/1 i0 70/! 60H the word current is shown as the ordinate. As is underodium(!y)pophosphite (g) gig 4500.2 2 stood in the art, the bit current is the current applied 53:22am diameter (mils) avg-5 1,1 down the plated wire during a write cycle, whereas the word current is applied to the strap positioned orthogol5 TABLE III 25; MIL WIRE 5 MIL WIRE Range Preferred Range Preferred Cleaner Current 800-2400 I600 400-1200 800 (malcm Cleaner Temp. 50-70 60 50-70 C 60 Copper Current 160-1900 900 80-l 200 900 (ma/cm) Copper Temp. 2545 25-45 35 Copper Flow 300-600 450 300-600 450 (Ml/min) Permalloy Current For 8-l6ma I90 For 22-36ma 220 (ma/cm per cell per cell l30-260 l70-300 Temp. 50-60 53 50-60 53 Flow 600-1000 800 600-1000 800 (ml/min) Annealing Temp. 300-370 350 330470 350 l C) Wire Speed 22-22 14 12-22 14 (in/min) Bias Current 100-400 300 600-900 750 The film is deposited at a thickness of between 4K-7K A. The resulting magnetic film deposited on the uniformly rough surface would analyze by weight in the range of about 76-80% Ni, l7-l8% Fe, 2-5% Co and with the composition nonmagnetostrictive. Non-magnetostrictive wire is an important property for plated wire manufacture because of its mechanical flexibility. In the event that the wire were made with positive or negative magnetostriction, torsion would cause large changes in its magnetic behavior.

The cell construction utilized at stations 12, 16, 18 and 20 is fully disclosed in U.S. Pat. No. 3,682,185. The cell disclosed therein is designed to maintain compositional uniformity and thickness along the length of the wire and around the circumference at stations 18 and 20. In the present invention, the plating cell is 2-3 inches across, however, the length of the active plating chamber is approximately 1% inches. It should be noted hereat that although one magnetic plating cell is shown in FIG. 1, several cells may be utilized. The number of cells used is a function of the plating speed and in the preferred embodiment of 14 inches/min, two cells are utilized at the respective stations 18 and 20.

Referring again to FIG. 2, the bias current is shown as flowing through the wire in addition to the electroclean, copper deposition and magnetic plating currents. The bias current is utilized to orient the magnetimil to the plated wire. The word strap is energized at the same time as the plated wire is energized for a write cycle, whereas the word strap alone is energized during a read cycle. The single write switching threshold output is the locus of coincident word and bit currents which are required to write so that a certain output level is achieved on reading with the same word current. The upper limit of the word current shown on FIG. 5 is where the DRO (destructive read-out) is obtained and is produced by exceeding the NDRO limit of the wire. The upper limit of the bit current is set by the wall motion threshold and is the level of bit current where the domain walls between oppositely magnetized bits move along the wire under the influence of the bit field. Such wall motion will cause magnetization reversal of some bits along the wire and loss of information. The operating margin for a write cycle is the difference between the Bit Current Disturb Line (bit disburbance caused by the bit current alone) and the single write threshold curve. The operating point of the memory at any given level of word current must lie between these limits. The operating window" in which the operating point may lie must also be located between the two curves.

In the prior art plated wire manufacture, the width of the margin between the single write threshold and the Bit Current Disturb line has been relatively narrow. This margin is shown as a difference between the prior art single write threshold curve (dotted line) and the Bit Current Disturb. Therefore, in the prior art, these curves have not been sufficiently separated and the operating window" has been small. Accordingly, plated wires made in accordance with the prior art technique have a low manufacturing yield because in many wires the bit current operating margin shown in FIG. 5 is smaller than that which is required for memory operation.

Moreover, it has been the desire of those skilled in the art to make the limits of the single write threshold and the Bit Current Disturb further apart so that the required operating window" becomes even larger. The instant invention has provided a larger window by effectively moving the single write threshold curve further to the left (i.e., the solid curve line). This has opened up the margin between the two curves shown in FIG. 5 and as a result higher production yield is attained as well as better utilization of the wire. Thus, the wires made in accordance with the invention have larger operating margin so that they can withstand a greater variation in the circuitry connected to the word strap and the bit line. In other words, even though the circuitry connected to the plated wire memory degrades due to age and as a result of other variables so that the operating point shifts, nevertheless the wire will continue to operate satisfactorily because of the greater operating window provided.

Another improvement obtained by the present invention has been the greater uniformity of magnetic properties along the length of the wire and may be appreciated by referring to FIG. 5. FIG. 5 depicts the magnetic properties of a single bit. It has been found that the magnetic characteristic of the bitsalong the wire have in general the same locus of points as the bit depicted, thereby providing a high degree of uniformity in terms of wire characteristics as a function of the bit position along the wire.

What is claimed is:

l. The method of manufacturing an improved plated wire memory device having a smooth wire substrate and a caviar intermediate layer, the improvement comprising the steps of:

a. moving said smooth wire with a caviar intermediate layer continuously through a plating cell;

b. moving an electrolyte through said cell in order to plate a magnetic coating on said caviar layer wherein said electrolyte consists essentially of an aqueous solution of nickel sulfamate, iron sulfamate, cobalt sulfate, boric acid and trisodium salt of napthalene tri-sulfonic acid, and sodium hypophosphite,

the nickel to iron weight ratio in said electrolyte 4. The method of manufacturing an improved plated wire memory device in accordance with claim 3 wherein said electrolyte is applied to said caviar surface with a current density of about -300 milliamperes per square centimeter.

5. The method of manufacturing an improved plated wire memory device in accordance with claim 4 wherein said electrolyte is applied at a temperature of about 5060 C and a flow rate of about 600-l,000 milliliters per minute.

6. The method of manufacturing an improved plated wire memory device, having a smooth wire substrate and a caviar intermediate layer the improvement comprising the steps of:

a. moving continuously said smooth wire with a caviar intermediate layer through a plating cell b. providing an electrolyte for said cell in order to plate a magnetic coating on said caviar layer, said electrolyte comprising, for one liter of water; on the order of 290-350 grams of nickel sulfamate, 5.0-6.2 grams of ferrous sulfamate, 1.0-2.5 CoSO4. 7H O, 20-40 grams of boric acid, l0-20 grams of trisodium salt of napthalene tri-sulfonic acid, 2-4 grams of sulfamic acid, 0.04-0.20 grams of sodium hypophosphite,

c. said electrolyte being maintained at a pH in the range of 2.0-3.0 and a temperature of 50-60 C. 

1. THE METHOD OF MANUFACTURING AN IMPROVED PLATED WIRE MEMORY DEVICE HAVING A SMOOTH WIRE SUBSTRATE AND A CAVIAR INTERMEDIATE LAYER, THE IMPROVEMENT COMPRISING THE STEPS OF: A. MOVING SAID SMOOTH WIRE WITH A CAVIAR INTERMEDIATE LAYER CONTINUOUSLY THROUGH A PLATING CELL; B. MOVING AN ELECTRLYTE THROUGH SAID CELL IN ORDER TO PLATE A MAGNETIC COATING ON SAID CAVIAR LAYER WHEREIN SAID ELECTROLYTE CONSISTS ESSENTIALLY OF AN AQUEOUS SOLUTION OF NICKEL SULFAMATE, IRON SULFAMATE, COBALT SULFATE, BORIC ACID AND TRISODIUM SALT OF NAPTHALENE TRI-SULFONIC ACID, AND SODIUM HYPOPHOSPHITE, THE NNICKEL TO IRON WEIGHT RATIO IN SAID ELECTRLYTE BEING IN THE RANGE OF 50/1 TO 70/1.
 2. The method of manufacturing an improved plated wire memory device in accordance with claim 1 wherein the amount of nickel sulfamate and iron sulfamate in said electrolyte are respectively in the range of 290-350 and 5.0-6.2 grams per liter.
 3. The method of manufacturing an improved plated wire memory device in accordance with claim 2 wherein the amount of sodium hypophosphite in said electrolyte is in the range of 0.04-0.20 grams per liter.
 4. The method of manufacturing an improved plated wire memory device in accordance with claim 3 wherein said electrolyte is applied to said caviar surface with a current density of about 130-300 milliamperes per square centimeter.
 5. The method of manufacturing an improved plated wire memory device in accordance with claim 4 wherein said electrolyte is applied at a temperature of about 50*-60* C and a flow rate of about 600-1,000 milliliters per minute.
 6. The method of manufacturing an improved plated wire memory device, having a smooth wire substrate and a caviar intermediate layer the improvement comprising the steps of: a. moving continuously said smooth wire with a caviar intermediate layer through a plating cell b. providing an electrolyte for said cell in order to plate a magnetic coating on said caviar layer, said electrolyte comprising, for one liter of water, on the order of 290-350 grams of nickel sulfamate, 5.0-6.2 grams of ferrous sulfamate, 1.0-2.5 CoSO4. 7H2O, 20-40 grams of boric acid, 10-20 grams of trisodium salt of napthalene tri-sulfonic acid, 2-4 grams of sulfamic acid, 0.04-0.20 grams of sodium hypophosphite, c. said electrolyte being maintained at a pH in the range of 2.0-3.0 and a temperature of 50*-60* C. 